From Q-bits to NAND flash, small integrated electronic devices are shaping the future. The 2017 IEEE IEDM Conference was a great place to get a view of the advances that will power future electronics, including memory and storage. I will cover a few highlights from the 2017 conference including 3D chips, emerging memories and data aware memories. This is a major IEEE conference on electronic technology and processes and included participants from international research institutions such as LETI in France and IMEC in Belgium as well as major semiconductor manufacturers.
J.Y.C. Sun from TSMC said that by 2020 we will have chips with 50 billion transistors per die. He said that this is still less complexity than the brain where the 20 million neurons are equivalent to about 1 trillion transistors. He also said that with 3D X 3D superchips (such as those being developed by nVIDIA and other companies) we could have collections of 200 billion transistors, at which point we are approaching the complexity of the human brain.
Building advanced 3D structures on-chip as well as between multiple stacked chips is a major driver of new technology. Some operations of a 3D nanosystem chip are shown below. There were sessions on 3D integration and packaging at the IEDM.
The complexity available in very small devices will enable ubiquitous computing, with very smart devices running AI on end products (like consumer devices). Emerging non-volatile memories will be part of this, enabling neuromorphic computing for on-device machine learning that furthers the capabilities of today’s neural networks. Neuromorphic computing was pioneered by Prof. Carver Mead in the 1980’s. In this model learning is a pattern of energy with minimum energy states acting as attractors to converged solutions.
Resistive RAM (ReRAM) devices are a popular technology to use for neuromorphic memory chips because it can act as a synaptic device. Many conference papers revealed various ways to improve the characteristics of these memories, such as better selectors (to reduce the sneak current) and subtle processing steps. SK Hynix presented a paper on cross-point 23nm RERAM with arsenic doping to create threshold switching behavior.
A paper from Global Foundries discussed a 7nm CMOS technology for high performance computing and mobile devices. Ken Takeuchi from Chuo University gave a talk about providing additional processing capability in a NAND flash controller. The controller recognizes the application-specific important data and stored it in reliable memory cells. In this method, although the precision of the circuits themselves is reduced, the application level accuracy, e.g. inference results of deep learning are not degraded because pattern matching with the neural network is error-tolerant.
This is an example of how approximate computing can be used to provide useful functions in a smaller and more energy efficient processor-here used inside of a memory/storage device. The author says that future data centers will adopt disaggregated hybrid storage composed of CPUs, DRAMS, storage controllers, storage class memories (SCMs) and flash memory.
For the second year the IEEE Magnetics Society hosted an MRAM poster session at the conference, that was well attended and featured much interesting research on various approaches to MRAM and related technologies. An invited talk by Kang and Park from Qualcomm Technologies said that, “MRAM is poised for a unified memory subsystem that can revamp the architectures of emerging ultra low energy systems such as Internet-of-Things (IoT) and wearable devices.” They also said that MRAM could transform computing-centric architectures. The fast write and read speeds of perpendicular STT-MTJ (spin-tunnel torque magnetic tunnel junction) MRAM devices allows them to be used directly with processors like today’s SRAM and DRAM.
This allows using one MRAM memory to replace an SRAM and flash architecture used in many IoT applications and thus reduces the flow of information between memories and saving power (especially important in battery powered applications). MRAMs don’t require static power, using them rather than SRAMs saves even more power. MRAM bitcells are about 25-30% of the size of SRAM bitcell, so using MRAMs also saves die space. The authors said that with the use of perpendicular MTJs data retention can be tailored high enough to support 10-20 years of data retention at 125 degrees and higher, making them suitable for applications such as automobiles.
Furthermore, he said that with circuit simplifications that MRAM should be recognized as a cost-competitive memory, particularly for embedded applications. However, MRAM is not at the maturity level to become cost-comparable with high-density commodity DRAM. So, they suggest application-driven custom standalone MRAM, which is less expensive than eMRAM (embedded MRAM).
The future of electronic chip-based devices for the data center as well as embedded applications, such as in computer and industrial devices is going 3D. Multiple devices per chip and multiple stacked chips will dominate many applications. In addition, emerging memory technologies such as various resistive memories as well as MRAM will enable storage class memories and lower power, long duration IoT and other growing applications.
